The semiconductor industry has witnessed dramatic improvements during the last three decades. In the early 70's, an integrated circuit (IC) manufacturer was able to cram only several thousand transistors onto a silicon chip. For example, Intel's 8-bit CPU 8080 has only about 5000 transistors. Today, it is possible to fabricate tens of millions of transistors on a single chip. For instance, Intel's Pentium 4 CPU hosts as many as 42 millions transistors. These transistors are electrically connected to each other through various metallic interconnects to accomplish many complex functionalities.
Any operation conducted by an IC can be essentially reduced to a simplified model in which a signal change at an input terminal of the IC triggers a signal change at an output terminal. For example, a flip-flop is a circuit that stores either a 0 or 1 at its output terminal. The stored value changes from 0 to 1 or 1 to 0 only when there is a signal change at its input terminal. Ideally, if there is no delay between the two signal changes at the input and output ends of an IC, an electronic device made of such an IC, e.g., a computer, can operate infinitely fast. The reality, however, is that there is a time delay between the input and output terminals of any circuit. Specifically, there are two types of sub-circuit level transmission delays contributing to the circuit-level time delay. One of them is the transistor transmission delay which is the time it takes to turn an individual transistor on/off, and the other is the interconnect transmission delay which is the time it takes a signal to travel through a metallic interconnect that connects one transistor's output terminal to another one's input terminal. As a result, the speed of an IC that comprises millions of transistors and interconnects is substantially determined by the sum of the two types of transmission delays occurring at transistor and interconnect levels. Therefore, important research topics of IC manufacture are how to determine the transmission delay of an individual interconnect and how to reduce such delay.
The transmission delay of a metallic interconnect can be estimated by τ≈RC, where R is the interconnect's parasitic resistance and C is its parasitic capacitance. Clearly, reduction of either of the two parameters can result in a smaller transmission delay. Since low resistivity metals such as copper and low permittivity (low-k) dielectric materials reduce the parasitic resistance and capacitance, respectively, of a metallic interconnect, they are being used more and more widely in IC manufacture.
However, it is not enough simply to reduce a metallic interconnect's parasitic resistance and capacitance from the perspective of circuit design. It is even more critical to know the exact resistance and capacitance values of each unique type of interconnect existing in a circuit to achieve better overall circuit performance. For example, timing analysis is an important step to guarantee that an IC operate in a predefined logical manner so as to produce a desired result. The accuracy of timing analysis directly relies upon the accuracy of transmission delay estimation at the metallic interconnect level, which, as suggested above, depends upon the accuracy of each interconnect's resistance and capacitance measurement.
An accurate measurement of an interconnect's resistance and capacitance also plays a critical role in solving an important IC manufacturing problem, process variation. Process variation refers to the phenomenon that the processing parameters, e.g., temperature in a wafer processing chamber, often change with time during chip fabrication. Such change may affect the uniformity and quality of chips being processed. One way of monitoring such process variation is to fabricate interconnect test structures on the wafer and measure their resistance and/or capacitance periodically. Advantageously, such test structures can be fabricated on the scribe line which is an area on the wafer between adjacent chips that is left empty of circuitry where a saw can pass and slice the chips apart.
Therefore, in both performing timing analysis and monitoring process variation, it is necessary to know both the parasitic resistance and capacitance of an interconnect. The conventional approach is to measure the two parameters separately. For example, the resistance may be measured at one interconnect and the capacitance at another interconnect. An implicit assumption of such approach is that the two interconnects are substantially similar to each other such that they are inter-changeable for the purpose of resistance and capacitance measurements, even if they are not spatially close to each other. Unfortunately, as discussed below in connection with FIG. 1, this assumption has a serious defect in the case of copper interconnects.
FIG. 1 illustrates the major steps in forming copper interconnects in a layer of inter-layer dielectric (ILD) material 100 during chip fabrication. First, a mask 110 made of photoresist material is positioned on top of ILD layer 100 (FIG. 1(a)). Mask 110 has an embedded pattern that exposes some surface areas of ILD layer 100 for etching. Next, certain etchants etch away some dielectric material from ILD layer 100 (FIG. 1(b)). After that, mask 110 is removed from the surface of ILD layer 100, leaving trenches of various shapes in the ILD layer 100 (FIG. 1(c)). For illustrative purposes, trenches 112 and 115 have an identical cross section, and the cross sections of trenches 113, 114 and 116 are also substantially similar to each other. The widths of trenches 112 and 115 are significantly larger than that of the other trenches. Compared with relatively isolated trenches 112, 115 and 116, trenches 113 and 114 are immediately next to each other. After removing mask 110, a copper layer 120 is deposited on top of ILD layer 100 to fill trenches 112–116 and cover the layer's remaining surface (FIG. 1(d)). Finally, the copper layer on the remaining surface is removed through a process called chemical/mechanical planarization (CMP). CMP is a process whereby a chemical reaction increases the mechanical removal rate of a material such as copper. The copper strips left in the trenches by CMP are metallic interconnects 122–126 that transmit signals from one transistor to another.
Mainly due to the hardness difference between the ILD material (e.g., SiO2) and the copper, CMP often causes an indentation on the surface of metallic interconnects 122–126, which is also referred to as dishing effect. The extent of dishing effect, which is measured by the distance between an interconnect's surface and the upper surface of ILD layer 100's, varies from one interconnect to another. For example, as shown in FIG. 1(e) interconnect 125's dishing effect h3 is larger than interconnect 122's dishing effect h1 even though their hosting trenches have the same dimension. This may be caused by the surface non-uniformity of the tool that conducts CMP. Interconnects 123 and 124's dishing effect h2 is more significant than interconnect 126's dishing effect h4. This is because that the two interconnects are so close, which makes it easy to erase the in-between ILD material. As a result, different interconnects in different trenches of the same width and depth may have different parasitic capacitances and resistances.
In view of the aforementioned problems, it would be desirable to develop a structure for measuring interconnect resistance and capacitance at the same or similar location so as to achieve to an accurate estimate of interconnect transmission delay or process variation.